Copper damascene technology has become the choice of metal interconnect technology in deep submicron silicon device manufacturing. Damascene structures used in integrated circuit technology comprise layers of conductor formed within layers of insulator material such that the top surfaces of the two layers are coplanar. The insulator material is patterned and etched to create vias and trenches which are then filled with conductive material.
Dual damascene processing involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The entire opening is then filled with a conductive material to simultaneously form a runner and a contact or via connecting runners in different levels of interconnect. An advantage of the dual damascene process is that the contact or via and the overlying trench (metal line) are formed simultaneously.
Excess conductive material on the surface of the inter-metal dielectric layer is then removed by a process called Chemical-Mechanical Polishing (CMP) which involves polishing with a slurry comprising abrasive particles suspended in a chemically reactive liquid. Surfaces subjected to CMP are simultaneously exposed to both chemical and mechanical polishing on a rotating platen. The removal rate of material from a surface undergoing CMP is dependent on a number of factors, including the materials being removed, the hardness and size of the slurry particles, the reactivity of the slurry liquid, the flow rate at which slurry is introduced, the rotational speed of the platen, and the pressure between the surface being polished and the platen.
FIG. 1 illustrates a step in a conventional integrated circuit fabrication sequence wherein a dual damascene metallization level, e.g., formed by electroplated copper, has been formed in a low constant (“low-k”) dielectric material 10. The low-k dielectric material 10 is formed over a relatively high-k etch stop layer, while the upper surface of the low-k dielectric material 10 is typically protected from damage during the manufacturing process by formation of an overlying capping layer (e.g., a silicon oxide, silicon nitride, silicon carbide or a combination thereof).
As illustrated in FIG. 1, after being planarized by CMP, the metal runners 12 exhibit a characteristic dishing effect along an upper surface of each runner. This is in contrast as shown to the relatively planar disposition of the hard dielectric capping layer.
Although CMP has been successfully implemented for copper damascene technology, it is becoming more difficult to fabricate finer metal line widths and pitches due to formation of the dished metal surfaces. The amount of dishing after CMP may vary based on metal geometry and pattern density. In practice it is often necessary to continue CMP beyond the stage illustrated in FIG. 1 in order to remove residual copper and barrier metal traces from regions along the surface which may be distant from the trenches. With subsequent formation of a next level of interconnect, the shape of the dished copper surface 12 is passed on to the overlying inter-metal dielectric layer stack.
Generally, it has been difficult to limit the extent of dishing due to the combination of a relatively soft metal such as copper and a relatively hard dielectric capping layer covering the low-k dielectric material during the CMP process. Thus, as can be seen, a need exists for an improved method of forming damascene metallization levels in low-k dielectric layers with reduced dishing.